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LTC6946 1 6946fa typical application features description ultralow noise and spurious 0.37ghz to 5.7ghz integer-n synthesizer with integrated vco the ltc ? 6946 is a high performance, low noise, 5.7ghz phase-locked loop (pll) with a fully integrated vco, including a reference divider, phase-frequency detector (pfd) with phase-lock indicator, ultralow noise charge pump, integer feedback divider, and vco output divider. the charge pump contains selectable high and low voltage clamps useful for vco monitoring. the integrated low noise vco uses no external components. it is internally calibrated to the correct output frequency with no external system support. the part features a buffered, programmable vco output divider with a range of 1 through 6, providing a wide frequency range. LTC6946-3 pll phase noise applications n low noise integer-n pll with integrated vco n C226dbc/hz normalized in-band phase noise floor n C274dbc/hz normalized in-band 1/f noise n C157dbc/hz wideband output phase noise floor n excellent spurious performance n output divider (1 to 6, 50% duty cycle) n output buffer muting n low noise reference buffer n charge pump current adjustable from 250a to 11.2ma n configurable status output n spi compatible serial port control n pllwizard? software design tool support n wireless base stations (lte, wimax, w-cdma, pcs) n broadband wireless access n military and secure radio n test and measurement l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and pllwizard is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. offset frequency (hz) C140 phase noise (dbc/hz) C130 C110 C90 C80 100 10k 100k 10m 40m 6946 ta01b C150 1k 1m C100 C120 C160 rms noise = 0.61 rms jitter = 296fs f rf = 5.7ghz f pfd = 10mhz bw = 85khz gnd v cp + cp v ref + ref C ref + bb v rf + rf + rf C gnd mute v refo + refo stat cs sclk sdi sdo v d + v vco + gnd cm a cm b cm c gnd tb tune LTC6946-3 0.01f 0.01f 2.2f 0.01f 100pf 0.01f 68nh 68nh 1f 3.3v 3.3v 4.7nf 57nf 100pf unused output is available for other use rf input signal to if processing lo if rf 0.01f 470pf 0.1f 0.1f 3.3v 6946 ta01a 3.3v 3.3v + 470pf 51.1 50 spi bus 10mhz 15 97.6 5v frequency coverage options LTC6946-1 LTC6946-2 LTC6946-3 vco frequency (ghz) 2.240 to 3.740 3.080 to 4.910 3.840 to 5.790 o div = 1 2.240 to 3.740 3.080 to 4.910 3.840 to 5.790 o div = 2 1.120 to 1.870 1.540 to 2.455 1.920 to 2.895 0 div = 3 0.747 to 1.247 1.027 to 1.637 1.280 to 1.930 o div = 4 0.560 to 0.935 0.770 to 1.228 0.960 to 1.448 o div = 5 0.448 to 0.748 0.616 to 0.982 0.768 to 1.158 o div = 6 0.373 to 0.623 0.513 to 0.818 0.640 to 0.965 5.7ghz wideband receiver
LTC6946 2 6946fa pin configuration absolute maximum ratings supply voltages v + (v ref + , v refo + , v rf + , v d + ) to gnd ..................3.6v v cp + , v vco + to gnd .............................................5.5v voltage on cp pin ................. gnd C 0.3v to v cp + + 0.3v voltage on all other pins ..........gnd C 0.3v to v + + 0.3v operating case temperature range (t c ) (note 2) .................................................. C40c to 105c operating junction temperature ........................... 125c storage temperature range .................. C65c to 150c (note 1) 9 10 top view 29 gnd ufd package 28-lead (4mm s 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 v refo + refo stat cs sclk sdi sdo v d + v vco + gnd cm a cm b cm c gnd tb tune ref C ref + v ref + cp v cp + gnd mute gnd rf C rf + v rf + bb 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, jc = 7c/w, exposed pad (pin 29) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking package description case temperature range LTC6946iufd-1#pbf LTC6946iufd-1#trpbf 69461 28-lead (4mm 5mm) plastic qfn C40c to 105c LTC6946iufd-2#pbf LTC6946iufd-2#trpbf 69462 28-lead (4mm 5mm) plastic qfn C40c to 105c LTC6946iufd-3#pbf LTC6946iufd-3#trpbf 69463 28-lead (4mm 5mm) plastic qfn C40c to 105c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ available options vco frequency range (ghz) package style output frequency range vs output divider setting (ghz) qfn-28 (ufd28) 0 div = 6 0 div = 5 0 div = 4 0 div = 3 0 div = 2 0 div = 1 2.240 to 3.740 LTC6946iufd-1 0.373 to 0.623 0.448 to 0.748 0.560 to 0.935 0.747 to 1.247 1.120 to 1.870 2.240 to 3.740 3.080 to 4.910 LTC6946iufd-2 0.513 to 0.818 0.616 to 0.982 0.770 to 1.228 1.027 to 1.637 1.540 to 2.455 3.080 to 4.910 3.840 to 5.790 LTC6946iufd-3 0.640 to 0.965 0.768 to 1.158 0.960 to 1.448 1.280 to 1.930 1.920 to 2.895 3.840 to 5.790 overlapping frequency bands
LTC6946 3 6946fa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25c. v ref + = v ref0 + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v unless otherwise specified (note 2). all voltages are with respect to gnd. symbol parameter conditions min typ max units reference inputs (ref + , ref C ) f ref input frequency l 10 250 mhz v ref input signal level single ended l 0.5 2 3.3 v p-p input slew rate l 20 v/s input duty cycle 50 % self-bias voltage l 1.65 1.85 2.25 v input resistance differential l 6.2 8.4 11.6 k input capacitance differential 3 pf reference output (refo) f refo output frequency l 10 250 mhz p refo output power f refo = 10mhz, r load = 50 l C0.2 3.2 dbm output impedance, disabled 800 vco f vco frequency range LTC6946-1 (note 3) LTC6946-2 (note 3) LTC6946-3 (note 3) l l l 2.240 3.080 3.840 3.740 4.910 5.790 ghz ghz ghz k vco tuning sensitivity LTC6946-1 (notes 3, 4) LTC6946-2 (notes 3, 4) LTC6946-3 (notes 3, 4) 4.7 to 7.2 4.7 to 7.0 4.0 to 6.0 %hz/v %hz/v %hz/v rf output (rf + , rf C ) f rf output frequency l 0.373 5.790 ghz o output divider range all integers included l 16 output duty cycle 50 % output resistance single ended, each output to v rf + l 111 136 159 output common mode voltage l 2.4 v rf + v p rf(se) output power, single ended, f rf = 900mhz rfo[1:0] = 0, r z = 50, lc match rfo[1:0] = 1, r z = 50, lc match rfo[1:0] = 2, r z = 50, lc match rfo[1:0] = 3, r z = 50, lc match l l l l C9.7 C6.8 C3.9 C1.2 C6.0 C3.6 C0.4 2.3 dbm dbm dbm dbm output power, muted r z = 50, single ended, f rf = 900mhz, o = 2 to 6 l C60 dbm mute enable time l 110 ns mute disable time l 170 ns phase/frequency detector f pfd input frequency l 100 mhz lock indicator, available on the stat pin and via the spi-accessible status register t lww lock window width lkwin[1:0] = 0 lkwin[1:0] = 1 lkwin[1:0] = 2 lkwin[1:0] = 3 3.0 10.0 30.0 90.0 ns ns ns ns t lwhys lock window hysteresis increase in t lww moving from locked state to unlocked state 22 % charge pump i cp output current range 12 settings (see table 5) 0.25 11.2 ma output current source/sink accuracy all settings v cp = v cp + /2 6 % output current source/sink matching i cp = 250a to 1.4ma, v cp = v cp + /2 i cp = 2.0ma to 11.2ma, v cp = v cp + /2 3.5 2 % %
LTC6946 4 6946fa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25c. v ref + = v ref0 + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v unless otherwise specified (note 2). all voltages are with respect to gnd. symbol parameter conditions min typ max units output current vs output voltage sensitivity (note 5) l 0.1 0.5 %/v output current vs temperature v cp = v cp + /2 l 170 ppm/c output hi-z leakage current i cp = 700a, cpclo = cpchi = 0 (note 5) i cp = 11.2ma, cpclo = cpchi = 0 (note 5) 0.5 5 na na v clmp(lo) low clamp voltage cpclo = 1 0.84 v v clmp(hi) high clamp voltage cpchi = 1, referred to v cp + C0.96 v v mid mid-supply output bias ratio referred to (v cp + C gnd) 0.48 v/v reference (r) divider r divide range all integers included l 1 1023 counts vco (n) divider n divide range all integers included l 32 65535 counts digital pin specifications v ih high level input voltage mute, cs, sdi, sclk l 1.55 v v il low level input voltage mute, cs, sdi, sclk l 0.8 v v ihys input voltage hysteresis mute, cs, sdi, sclk 250 mv input current mute, cs, sdi, sclk l 1 a i oh high level output current sdo and stat, v oh = v d + C 400mv l 1.4 2.3 ma i ol low level output current sdo and stat, v ol = 400mv l 1.8 2.6 ma sdo hi-z current l 1 a digital timing specifications (see figures 7 and 8) t ckh sclk high time l 25 ns t ckl sclk low time l 25 ns t css cs setup time l 10 ns t csh cs high time l 10 ns t cs sdi to sclk setup time l 6n s t ch sdi to sclk hold time l 6n s t do sclk to sdo time to v ih /v il /hi-z with 30pf load l 16 ns power supply voltages v ref + supply range l 3.15 3.3 3.45 v v refo + supply range l 3.15 3.3 3.45 v v d + supply range l 3.15 3.3 3.45 v v rf + supply range l 3.15 3.3 3.45 v v vco + supply range l 4.75 5.0 5.25 v v cp + supply range l 4.0 5.25 v power supply currents i dd v d + supply current digital inputs at supply levels l 250 a i cc(5v) sum v cp + , v vco + supply currents i cp = 11.2ma i cp = 1.0ma pdall = 1 l l l 49 27 405 61 37 660 ma ma a i cc(refo) v refo + supply currents refo enabled, r z = l 7.8 9.0 ma
LTC6946 5 6946fa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t c = 25c. v ref + = v ref0 + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v unless otherwise specified (note 2). all voltages are with respect to gnd. symbol parameter conditions min typ max units i cc (3.3v) sum v ref + , v rf + supply currents rf muted, od[2:0] = 1 rf enabled, rfo[1:0] =0, od[2:0] = 1 rf enabled, rfo[1:0] = 3, od[2:0] = 1 rf enabled, rfo[1:0] =3, od[2:0] = 2 rf enabled, rfo[1:0] =3, od[2:0] = 3 rf enabled, rfo[1:0] =3, od[2:0] = 4 to 6 pdall = 1 l l l l l l l 63 74 83 100 105 110 195 72 82 92 111 117 122 340 ma ma ma ma ma ma a phase noise and spurious l m phase noise (LTC6946-1, f vco = 3.0ghz, f rf = 3.0ghz, od[2 :0] = 1 (note 6)) 10khz offset 1mhz offset 40mhz offset C80 C130 C157 dbc/hz dbc/hz dbc/hz phase noise (LTC6946-2, f vco = 4.0ghz, f rf = 4.0ghz, od[2 :0] = 1 (note 6)) 10khz offset 1mhz offset 40mhz offset C77 C127 C156 dbc/hz dbc/hz dbc/hz phase noise (LTC6946-3, f vco = 5.0ghz, f rf = 5.0ghz, od[2 :0] = 1 (note 6)) 10khz offset 1mhz offset 40mhz offset C75 C126 C155 dbc/hz dbc/hz dbc/hz phase noise (LTC6946-3, f vco = 5.0ghz, f rf = 2.50ghz, od[2 :0] = 2 (note 6)) 10khz offset 1mhz offset 40mhz offset C81 C132 C155 dbc/hz dbc/hz dbc/hz phase noise (LTC6946-3, f vco = 5.0ghz, f rf = 1.667ghz, od[2 :0] = 3 (note 6)) 10khz offset 1mhz offset 40mhz offset C84 C135 C156 dbc/hz dbc/hz dbc/hz phase noise (LTC6946-3, f vco = 5.0ghz, f rf = 1.25ghz, od[2 :0] = 4 (note 6)) 10khz offset 1mhz offset 40mhz offset C87 C138 C156 dbc/hz dbc/hz dbc/hz phase noise (LTC6946-3, f vco = 5.0ghz, f rf = 1.00ghz, od[2 :0] = 5 (note 6)) 10khz offset 1mhz offset 40mhz offset C89 C140 C157 dbc/hz dbc/hz dbc/hz phase noise (LTC6946-3, f vco = 5.0ghz, f rf = 0.833ghz, od[2 :0] = 6 (note 6)) 10khz offset 1mhz offset 40mhz offset C90 C141 C158 dbc/hz dbc/hz dbc/hz l m(norm) normalized in-band phase noise floor i cp = 11.2ma (notes 7, 8, 9) C226 dbc/hz l m(norm C 1/f) normalized in-band 1/f phase noise i cp = 11.2ma (notes 7, 10) C274 dbc/hz l m(ib) in-band phase noise floor (notes 7, 8, 9, 11) C99 dbc/hz integrated phase noise from 100hz to 40mhz (notes 8, 12) 0.17 rms spurious f offset = f pfd , pll locked (notes 8, 12, 13) C103 dbc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC6946i is guaranteed functional within the case operating temperature range from C40c to 105c ( jc = 7/w). note 3: valid for 1.60v tune 2.85v with part calibrated after a power cycle or software power-on-reset (por). note 4: based on characterization. note 5: for 0.7v v cp (v cp + C 0.7v). note 6: measured outside the loop bandwidth, using a narrowband loop, rfo[1:0] = 3. note 7: measured inside the loop bandwidth with the loop locked. note 8: reference frequency supplied by wenzel 501-04608a, f ref = 10mhz, p ref = 13dbm. note 9: output phase noise floor is calculated from normalized phase noise floor by l m(out) = C226 + 10log 10 (f pfd ) + 20log 10 (f rf /f pfd ). note 10: output 1/f phase noise is calculated from normalized 1/f phase noise by l m(out C 1/f) = C274 + 20log 10 (f rf ) C 10log 10 (f offset ). note 11: i cp = 11.2ma, f pfd = 250khz, filt[1:0] = 3, loop bw = 25khz; f rf = 900mhz, f vco = 2.7ghz (LTC6946-1), f vco = 3.6ghz (LTC6946-2), f vco = 4.5ghz (LTC6946-3). note 12: i cp = 11.2ma, f pfd = 1mhz, filt[1:0] = 3, loop bw = 40khz; f rf = 900mhz, f vco = 2.7ghz (LTC6946-1), f vco = 3.6ghz (LTC6946-2), f vco = 4.5ghz (LTC6946-3). note 13: measured using dc1705a.
LTC6946 6 6946fa typical performance characteristics charge pump sink current error vs voltage, output current charge pump source current error vs voltage, temperature charge pump sink current error vs voltage, temperature rf output power vs frequency (single ended on rf C ) charge pump source current error vs voltage, output current rf output hd2 vs output divide (single ended on rf C ) ref input sensitivity vs frequency ref0 output power vs frequency t c = 25c, v ref + = v refo + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, rfo[1:0] = 3,unless otherwise noted. refo phase noise frequency (mhz) 0 sensitivity (dbm) C15 C20 C25 C30 C35 C40 C45 C50 C55 200 6946 g01 50 100 150 250 175 25 75 125 225 bst = 1 filt = 0 105c 25c C40c frequency (mhz) 0 p out (dbm) 4 3 2 1 0 C1 C2 C3 C4 200 6946 g02 50 100 150 250 175 25 75 125 225 105c 25c C40c offset frequency (hz) C155 phase noise (dbc/hz) C150 C145 C140 100 10k 100k 1m 6946 g03 C160 1k p out = 1.45dbm f ref = 10mhz bst = 1 filt = 3 note 8 output voltage (v) 0 error (%) 1 3 5 4 6946 g04 C1 C3 0 2 4 C2 C4 C5 10.5 21.5 3 3.5 4.5 2.5 5 250a 1ma 11.2ma output voltage (v) 0 error (%) 1 3 5 4 6946 g05 C1 C3 0 2 4 C2 C4 C5 10.5 21.5 3 3.5 4.5 2.5 5 C40c 25c 105c i cp = 11.2ma output voltage (v) 0 error (%) 1 3 5 4 6946 g06 C1 C3 0 2 4 C2 C4 C5 10.5 21.5 3 3.5 4.5 2.5 5 250a 1ma 11.2ma output voltage (v) 0 error (%) 1 3 5 4 6946 g07 C1 C3 0 2 4 C2 C4 C5 10.5 21.5 3 3.5 4.5 2.5 5 C40c 25c 105c i cp = 11.2ma frequency (ghz) 0.5 p out (dbm) C2.5 0.5 1.0 1.5 1.5 3.53 4 4.5 6946 g08 C3.5 C0.5 C1.5 C3.0 0 C4.0 C1.0 C2.0 1 2 2.5 5 5.5 6 C40c 25c 105c LTC6946-3 l c = 68nh c s = 100pf f vco (ghz) 3.75 C50 hd2 (dbc) C45 C40 C35 C30 4.25 4.75 5.25 5.75 6946 g09 C25 C20 4.00 4.50 5.00 5.50 LTC6946-3, f rf = f vco /o l c = 68nh, c s = 100pf o = 3 o = 2 o = 1 o = 6 o = 4 o = 5
LTC6946 7 6946fa typical performance characteristics t c = 25c, v ref + = v refo + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, rfo[1:0] = 3,unless otherwise noted. LTC6946-1 vco tuning sensitivity LTC6946-2 vco tuning sensitivity LTC6946-3 vco tuning sensitivity rf output hd3 vs output divide (single ended on rf C ) mute output power vs f vco and output divide (single ended on rf C ) LTC6946-3 frequency step transient vs cpchi/lo LTC6946-1 vco phase noise LTC6946-2 vco phase noise LTC6946-3 vco phase noise f vco (ghz) 3.75 C40 hd3 (dbc) C35 C30 C25 C20 4.25 4.75 5.25 5.75 6946 g10 C15 C10 C5 4.00 4.50 5.00 5.50 LTC6946-3 l c = 68nh c s = 100pf f rf = f vco /o o = 6 o = 3 o = 2 o = 1 o = 5 o = 4 f vco (mhz) 3800 4050 p out at f vco /o (dbm) C70 C60 C50 5300 5550 6946 g11 C80 C90 4300 4550 4800 5050 5800 C100 C110 C40 LTC6946-3, l c = 68nh c s = 100pf, f rf = f vco /o o = 1 o = 4 o = 6 o = 5 o = 2 o = 3 time (s) 0 2.55 frequency (ghz) 2.60 2.65 2.70 2.75 2.80 2.85 50 100 150 200 6946 g12 250 calibratiion time cpchi, cpclo = 0 cpchi, cpclo = 1 f pfd = 1mhz f cal = 125khz bw = 40khz 100mhz step frequency (mhz) 2100 3.0 k vco (%hz/v) 3.5 4.5 5.0 5.5 8.0 6.5 2600 3100 6946 g13 4.0 7.0 7.5 6.0 3600 4100 frequency (mhz) 2800 3.0 k vco (%hz/v) 3.5 4.5 5.0 5.5 8.0 6.5 3300 3800 4300 6946 g14 4.0 7.0 7.5 6.0 4800 5300 frequency (mhz) 3500 2.5 k vco (%hz/v) 3.0 4.0 4.5 5.0 5500 7.0 6946 g15 3.5 4500 4000 6000 5000 6500 5.5 6.0 6.5 offset frequency (hz) 1k C100 phase noise (dbc/hz) C90 C80 C70 C60 100k 10k 1m 10m 40m 6946 g16 C110 C130 C150 C120 C140 C160 C50 C40 f vco = f rf = 3ghz offset frequency (hz) 1k C100 phase noise (dbc/hz) C90 C80 C70 C60 100k 10k 1m 10m 40m 6946 g17 C110 C130 C150 C120 C140 C160 C50 C40 f vco = f rf = 4ghz offset frequency (hz) 1k C100 phase noise (dbc/hz) C90 C80 C70 C60 100k 10k 1m 10m 40m 6946 g18 C110 C130 C150 C120 C140 C160 C50 C40 f vco = f rf = 5ghz
LTC6946 8 6946fa LTC6946-1 vco phase noise vs f vco , output divide (f offset = 1mhz) closed-loop phase noise, loop bandwidth = 40khz, LTC6946-1 LTC6946-1 vco phase noise vs f vco , output divide (f offset = 10khz) LTC6946-2 vco phase noise vs f vco , output divide (f offset = 10khz) LTC6946-2 vco phase noise vs f vco , output divide (f offset = 1mhz) closed-loop phase noise, loop bandwidth = 25khz, LTC6946-3 LTC6946-3 vco phase noise vs f vco , output divide (f offset = 10khz) LTC6946-3 vco phase noise vs f vco , output divide (f offset = 1mhz) LTC6946-2 supply current vs temperature typical performance characteristics t c = 25c, v ref + = v refo + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, rfo[1:0] = 3,unless otherwise noted. f vco (mhz) 2200 C105 phase noise (dbc/hz) C100 C95 C90 C85 C75 2450 2700 2950 3200 6946 g19 3450 3700 C80 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 5 o = 4 f vco (mhz) 3000 C100 phase noise (dbc/hz) C95 C90 C85 C80 C70 3250 3500 3750 4000 4250 6946 g20 4500 4750 C75 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 5 o = 4 f vco (mhz) 3800 phase noise (dbc/hz) C80 C75 C70 4550 5050 5800 6946 g21 C85 C90 C95 4050 4300 4800 5300 5550 f rf = f vco /o o = 1 o = 2 o = 3 o = 4 o = 6 o = 5 f vco (mhz) 2200 C150 phase noise (dbc/hz) C145 C140 C135 C125 2450 2700 2950 3200 6946 g22 3450 3700 C130 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 4 o = 5 f vco (mhz) 3000 C150 phase noise (dbc/hz) C145 C140 C135 C125 3250 3500 3750 4000 4250 6946 g23 4500 4750 C130 f rf = f vco /o f offset = 1mhz o = 1 o = 2 o = 3 o = 6 o = 5 o = 4 f vco (mhz) 3800 phase noise (dbc/hz) C130 C125 C120 4550 5050 5800 6946 g24 C135 C140 C145 4050 4300 4800 5300 5550 f rf = f vco /o o = 1 o = 2 o = 3 o = 4 o = 6 o = 5 offset frequency (hz) C140 phase noise (dbc/hz) C130 C110 C90 100 10k 100k 10m 40m 6946 g25 C150 1k 1m C100 C120 C160 rms noise = 0.169 f rf = 900mhz f pfd = 1mhz od = 3 f step = 333.3khz note 12 offset frequency (hz) C140 phase noise (dbc/hz) C130 C110 C90 100 10k 100k 10m 40m 6946 g26 C150 1k 1m C100 C120 C160 rms noise = 0.276 f rf = 900mhz f pfd = 250khz od = 5 f step = 50khz note 11 t c (c) C40 80 3.3v current (ma) 5v current (ma) 82 84 86 C20 0 20 40 6946 g27 60 88 90 81 83 85 87 89 45 47 49 51 53 55 46 48 50 52 54 80 100 pdrefo = 1 o = 1 rfo = 3 mute = 0 i cp = 11.2ma
LTC6946 9 6946fa LTC6946-3 spurious response f rf = 900mhz, f ref = 10mhz, f pfd = 1mhz, loop bw = 40khz LTC6946-3 spurious response f rf = 2200mhz, f ref = 10mhz, f pfd = 0.4mhz, loop bw = 28khz LTC6946-3 spurious response f rf = 5700mhz, f ref = 100mhz, f pfd = 1mhz, loop bw = 33khz typical performance characteristics t c = 25c, v ref + = v refo + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, rfo[1:0] = 3,unless otherwise noted. frequency offset (mhz in 10khz segments) C10 C105dbc C103dbc C111dbc C109dbc C3 C140 p out (dbm) C120 C100 C80 123 0 6946 g28 C2 C1 0 10 C60 C40 C20 rbw = 1hz vbw = 1hz notes 8, 13 frequency offset (mhz in 10khz segments) C10 C93dbc C94dbc C86dbc C88dbc C1.2 C140 p out (dbm) C120 C100 C80 0.4 0.8 1.2 0 6946 g29 C0.8 C0.4 0 10 C60 C40 C20 rbw = 1hz vbw = 1hz notes 8, 13 frequency offset (mhz in 10khz segments) C100 C101dbc C113dbc C96dbc C92dbc C3 C140 p out (dbm) C120 C100 C80 123 0 6946 g30 C2 C1 0 100 C60 C40 C20 rbw = 1hz vbw = 1hz note 13
LTC6946 10 6946fa pin functions v refo + (pin 1): 3.15v to 3.45v positive supply pin for refo circuitry. this pin should be bypassed directly to the ground plane using a 0.1f ceramic capacitor as close to the pin as possible. refo (pin 2): reference frequency output. this produces a low noise square wave, buffered from the ref differential inputs. the output is self-biased and must be ac-coupled with a 22nf capacitor. stat (pin 3): status output. this signal is a configurable logical or combination of the unlok, lok, alchi, alclo, thi and tlo status bits, programmable via the status register. see the operation section for more details. cs (pin 4): serial port chip select. this cmos input initi- ates a serial port communication burst when driven low, ending the burst when driven back high. see the operation section for more details. sclk (pin 5): serial port clock. this cmos input clocks serial port input data on its rising edge. see the operation section for more details. sdi (pin 6): serial port data input. the serial port uses this cmos input for data. see the operation section for more details. sdo (pin 7): serial port data output. this cmos three- state output presents data from the serial port during a read communication burst. optionally attach a resistor of >200k to gnd to prevent a floating output. see the operation section for more details. v d + (pin 8): 3.15v to 3.45v positive supply pin for serial port circuitry. this pin should be bypassed directly to the ground plane using a 0.1f ceramic capacitor as close to the pin as possible. mute (pin 9): rf mute. the cmos active-low input mutes the rf differential outputs while maintaining internal bias levels for quick response to de-assertion. gnd (pins 10, 17, 21): negative power supply (ground). these pins should be tied directly to the ground plane with multiple vias for each pin. rf C , rf + (pins 11, 12): rf output signals. the vco output divider is buffered and presented differentially on these pins. the outputs are open collector, with 136 (typical) pull-up resistors tied to v rf + to aid impedance matching. if used single ended, the unused output should be terminated to 50. see the applications information section for more details on impedance matching.
LTC6946 11 6946fa pin functions v rf + (pin 13): 3.15v to 3.45v positive supply pin for rf circuitry. this pin should be bypassed directly to the ground plane using a 0.01f ceramic capacitor as close to the pin as possible. bb (pin 14): rf reference bypass. this output must be bypassed with a 1.0f ceramic capacitor to gnd. do not couple this pin to any other signal. tune (pin 15): vco tuning input. this frequency control pin is normally connected to the external loop filter. see the applications information section for more details. tb (pin 16): vco bypass. this output must be bypassed with a 2.2f ceramic capacitor to gnd, and is normally connected to cm a , cm b and cm c with a short trace. do not couple this pin to any other signal. cm c , cm b , cm a (pins 18, 19, 20): vco bias inputs. these inputs are normally connected to tb with a short trace and bypassed with a 2.2f ceramic capacitor to gnd. do not couple these pins to any other signal. for best phase noise performance, do not place a trace between these pads underneath the package. v vco + (pin 22): 4.75v to 5.25v positive supply pin for vco circuitry. this pin should be bypassed directly to the ground plane using both 0.01f and 1f ceramic capaci- tors as close to the pin as possible. gnd (23): negative power supply (ground). this pin is attached directly to the die attach paddle (dap) and should be tied directly to the ground plane. v cp + (pin 24): 4.0v to 5.25v positive supply pin for charge pump circuitry. this pin should be bypassed directly to the ground plane using a 0.1f ceramic capacitor as close to the pin as possible. cp (pin 25): charge pump output. this bi-directional current output is normally connected to the external loop filter. see the applications information section for more details. v ref + (pin 26): 3.15v to 3.45v positive supply pin for reference input circuitry. this pin should be bypassed directly to the ground plane using a 0.1f ceramic capaci- tor as close to the pin as possible. ref + , ref C (pins 27, 28): reference input signals. this differential input is buffered with a low noise amplifier, which feeds the reference divider and reference buffer. they are self-biased and must be ac-coupled with 470pf capacitors. if used single ended, bypass ref C to gnd with a 470pf capacitor. gnd (exposed pad pin 29): negative power supply (ground). the package exposed pad must be soldered directly to the pcb land. the pcb land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance.
LTC6946 12 6946fa block diagram rf C 28 2 3 11 gnd 10 mute 9 rf + 12 v rf + 13 27 ref C refo 250mhz 100mhz 1 to 1023 1 to 6, 50% 32 to 65535 0.373ghz to 5.79ghz mute 1 v refo + ref + 26 v ref + r_div lock pfd o_div n_div b_div cal, alc control 2.24ghz to 3.74ghz (LTC6946-1) or 3.08ghz to 4.91ghz (LTC6946-2) or 3.84ghz to 5.79ghz (LTC6946-3) tune 15 cp v vco + gnd cm a cm b cm c gnd 250a to 11.2ma 25 22 21 20 19 18 17 24 v cp + 23 gnd 16 tb 6946 bd 14 bb serial port stat cs 7 sdo sdi sclk 8 v d + 6 5 4 operation the LTC6946 is a high performance pll complete with a low noise vco available in three different frequency range options. the output frequency range may be further extended by utilizing the output divider (see available op- tions table, for more details). the device is able to achieve superior integrated phase noise by the combination of its extremely low in-band phase noise performance and excellent vco noise characteristics. reference input buffer the plls reference frequency is applied differentially on pins ref + and ref C . these high impedance inputs are self-biased and must be ac-coupled with 470pf capacitors (see figure 1 for a simplified schematic). alternatively, the inputs may be used single ended by applying the refer- ence frequency at ref + and bypassing ref C to gnd with a 470pf capacitor. a high quality signal must be applied to the ref inputs as they provide the frequency reference to the entire pll. to achieve the parts in-band phase noise performance, apply 27 28 4.2k ref + ref C 4.2k 6946 f01 1.9v bst bias v ref + v ref + lowpass filt[1:0] figure 1. simplified ref interface schematic a cw signal of at least 6dbm into 50, or a square wave of at least 0.5v p-p with slew rate of at least 40v/s. additional options are available through serial port register h08 to further refine the application. bits filt[1:0] control the reference input buffers lowpass filter, and should be set based upon f ref to limit the references wideband noise. the filt[1:0] bits must be set correctly to reach the l m(norm) normalized in-band phase noise floor. see table 1 for recommended settings.
LTC6946 13 6946fa divide ratio. see the applications information section for the relationship between r and the f ref , f pfd , f vco and f rf frequencies. phase/frequency detector (pfd) the phase/frequency detector (pfd), in conjunction with the charge pump, produces source and sink current pulses proportional to the phase difference between the outputs of the r and n dividers. this action provides the necessary feedback to phase-lock the loop, forcing a phase align- ment at the pfds inputs. the pfd may be disabled with the cprst bit which prevents up and down pulses from being produced. see figure 3 for a simplified schematic of the pfd. the bst bit should be set based upon the input signal level to prevent the reference input buffer from saturating. see table 2 for recommended settings and the applications information section for programming examples. table 1. filt[1:0] programming filt[1:0] f ref 3 <20mhz 2n a 1 20mhz to 50mhz 0 >50mhz table 2. bst programming bst v ref 1 <2.0v p-p 0 2.0v p-p reference output buffer the reference output buffer produces a low noise square wave with a noise floor of C155dbc/hz (typical) at 10mhz. its output is low impedance, and produces 0dbm typical output power into a 50 load at 10mhz. larger output swings will result if driving larger impedances. the out- put is self-biased, and must be ac-coupled with a 22nf capacitor (see figure 2 for a simplified schematic). the buffer may be powered down by using bit pdrefo found in the serial port power register h02. 2 refo v refo + 800 6946 f02 figure 2. simplified refo interface schematic operation dq rst n div dq rst cprst up down 6946 f03 delay r div figure 3. simplified pfd schematic reference (r) divider a 10-bit divider, r_div, is used to reduce the frequency seen at the pfd. its divide ratio r may be set to any integer from 1 to 1023, inclusive. use the rd[9:0] bits found in registers h03 and h04 to directly program the r lock indicator the lock indicator uses internal signals from the pfd to measure phase coincidence between the r and n divider output signals. it is enabled by setting the lken bit in the serial port register h07, and produces both lock and unlock status flags, available through both the stat output and serial port register h00. the user sets the phase difference lock window time, t lww , for a valid lock condition with the lkwin[1:0] bits. see table 3 for recommended settings for different fpfd frequencies and the applications information section for examples.
LTC6946 14 6946fa operation table 3. lkwin[1:0] programming lkwin[1:0] t lww f pfd 0 3ns >5mhz 1 10ns 5mhz 2 30ns 1.7mhz 3 90ns 550khz the pfd phase difference must be less than t lww for the lokcnt number of successive counts before the lock indicator asserts the lock flag. the lkcnt[1:0] bits found in register h09 are used to set lokcnt depending upon the application. see table 4 for lkcnt[1:0] programming and the applications information section for examples. table 4. lkcnt[1:0] programming lkcnt[1:0] counts 03 2 1 128 2 512 3 2048 when the pfd phase difference is greater than t lww , the lock indicator immediately asserts the unlock status flag and clears the lock flag, indicating an out-of-lock condition. the unlock flag is immediately de-asserted when the phase difference is less than t lww . see figure 4 for more details. charge pump the charge pump, controlled by the pfd, forces sink (down) or source (up) current pulses onto the cp pin, which should be connected to an appropriate loop filter. see figure 5 for a simplified schematic of the charge pump. the output current magnitude i cp may be set from 250a to 11.2ma using the cp[3:0] bits found in serial port register h09. a larger i cp can result in lower in-band noise due to the lower impedance of the loop filter components. see table 5 for programming specifics and the applications information section for loop filter examples. table 5. cp[3:0] programming cp[3:0] i cp 0 250a 1 350a 2 500a 3 700a 4 1.0ma 5 1.4ma 6 2.0ma 7 2.8ma 8 4.0ma 9 5.6ma 10 8.0ma 11 11.2ma 12 to 15 invalid the cpinv bit found in register h0a should be set for applications requiring signal inversion from the pfd, such as for complex external loops using an inverting op amp. a passive loop filter as shown in figure 14 requires cpinv = 0. +t lww Ct lww unlock flag lock flag t = counts/f pfd 6946 f04 0 phase difference at pfd figure 4. unlock and lock timing 25 + C + C cp thi 0.9v v cp + v cp + tlo + C 0.9v 6946 f05 + C v cp + /2 cpmid cpup up cpdn down figure 5. simplified charge pump schematic
LTC6946 15 6946fa operation charge pump functions the charge pump contains additional features to aid in system start-up and monitoring. see table 6 for a summary. table 6. charge pump function bit descriptions bit description cpchi enable high voltage output clamp cpclo enable low voltage output clamp cpdn force sink current cpinv invert pfd phase cpmid enable mid-voltage bias cprst reset pfd cpup force source current cpwide extend current pulse width thi high voltage clamp flag tlo low voltage clamp flag the cpchi and cpclo bits found in register h0a enable the high and low voltage clamps, respectively. when cpchi is enabled and the cp pin voltage exceeds approximately v cp + C 0.9v, the thi status flag is set, and the charge pump sourcing current is disabled. alternately, when cpclo is enabled and the cp pin voltage is less than approximately 0.9v, the tlo status flag is set, and the charge pump sinking current is disabled. see figure 5 for a simplified schematic. the cpmid bit also found in register h0a enables a resis- tive v cp + /2 output bias which may be used to pre-bias troublesome loop filters into a valid voltage range. when using cpmid, it is recommended to also assert the cprst bit, forcing a pfd reset. both cpmid and cprst must be set to 0 for normal operation. the cpup and cpdn bits force a constant i cp source or sink current, respectively, on the cp pin. the cprst bit may also be used in conjunction with the cpup and cpdn bits, allowing a pre-charge of the loop to a known state, if required. cpup , cpdn, and cprst must be set to 0 to allow the loop to lock. the cpwide bit extends the charge pump output current pulse width by increasing the pfd reset paths delay value (see figure 3). cpwide is normally set to 0. table 7. bd[3:0] programming bd[3:0] b divide value f pfd (mhz) 0 8 <2.4 1 12 2.4 to 3.6 2 16 3.6 to 4.8 3 24 4.8 to 7.2 4 32 7.2 to 9.6 5 48 9.6 to 14 6 64 14 to 19 7 96 19 to 29 8 128 29 to 38 9 192 38 to 58 10 256 58 to 77 11 384 >77 12 to 15 invalid vco the integrated vco is available in one of three frequency ranges. the output frequency range may be further ex- tended by utilizing the output divider (see available options table, for more details). the wide frequency range of the vco, coupled with the output divider capability, allows the LTC6946 to cover an extremely wide range of continuously selectable frequencies. vco calibration the vco must be calibrated each time its frequency is changed by either f ref , the r divider, or n divider, but not the o divider (see the applications information section for the relationship between r, n, o, and the f ref , f pfd , f vco and f rf frequencies). the output frequency is then stable over the LTC6946s entire temperature range, regardless of the temperature at which it was calibrated, until the part is reset due to a power cycle or software power-on reset (por). the output of the b divider is used to clock digital calibra- tion circuitry as shown in the block diagram. the b value, programmed with bits bd[3:0], is determined according to equation 1. b f pfd 0.3mhz (1) the relationship between bits bd[3:0], the b value, and f pfd is shown in table 7.
LTC6946 16 6946fa operation the vco may be calibrated once the rd[9:0], nd[15:0], and bd[3:0] bits are written. the reference frequency f ref must also be present and stable at the ref inputs. a calibration cycle is initiated each time the cal bit is written to 1 (the bit is self-clearing). the calibration cycle takes between 12 and 14 cycles of the b divider output. vco automatic level control (alc) the vco uses an internal automatic level control (alc) algorithm to maintain an optimal amplitude on the vco resonator, and thus optimal phase noise performance. the user has several alc configuration and status reporting options as seen in table 8. table 8. alc bit descriptions bit description alccal auto enable alc during cal operation alcen always enable alc (overrides alccal, alcmon and alculok) alchi alc too high flag (resonator amplitude too high) alclo alc too low flag (resonator amplitude too low) alcmon enable alc monitoring for status flags only; does not enable amplitude control alculok auto enable alc when pll unlocked changes in the internal alc output can cause extremely small jumps in the vco frequency. these jumps may be acceptable in some applications but not in others. use the above table to choose when the alc is active. the alchi and alclo flags, valid only when the alc is active or the alcmon bit is set, may be used to monitor the resonator amplitude. the alc must be allowed to operate during or after a calibration cycle. at least one of the alccal, alcen or alculok bits must be set. vco (n) divider the 16-bit n divider provides the feedback from the vco to the pfd. its divide ratio n may be set to any integer from 32 to 65535, inclusive. use the nd[15:0] bits found in registers h05 and h06 to directly program the n divide ratio. see the applications information section for the relationship between n and the f ref , f pfd , f vco and f rf frequencies. output (o) divider the 3-bit o divider can reduce the frequency from the vco to extend the output frequency range. its divide ratio o may be set to any integer from 1 to 6, inclusive, outputting a 50% duty cycle even with odd divide values. use the od[2:0] bits found in register h08 to directly program the 0 divide ratio. see the applications information section for the relationship between o and the f ref , f pfd , f vco and f rf frequencies. rf output buffer the low noise, differential output buffer produces a dif- ferential output power of C6dbm to 3dbm, settable with bits rfo[1:0] according to table 9. the outputs may be combined externally, or used individually. terminate any unused output with a 50 resistor to v rf + . table 9. rfo[1:0] programming rfo[1:0} p rf (differential) p rf (single ended) 0 C6dbm C9dbm 1 C3dbm C6dbm 2 0dbm C3dbm 3 3dbm 0dbm each output is open collector with 136 pull-up resistors to v rf + , easing impedance matching at high frequencies. see figure 6 for circuit details and the applications infor- mation section for matching guidelines. the buffer may be muted with either the omute bit, found in register h02, or by forcing the mute input low. 12 11 6946 f06 v rf + v rf + rf + 136 136 rf C mute omute rfo[1:0] 9 mute figure 6. simplified rf interface schematic
LTC6946 17 6946fa operation serial port the spi-compatible serial port provides control and monitoring functionality. a configurable status output, stat, gives additional instant monitoring. communication sequence the serial bus is comprised of cs, sclk, sdi and sdo. data transfers to the part are accomplished by the serial bus master device first taking cs low to enable the LTC6946s port. input data applied on sdi is clocked on the rising edge of sclk, with all transfers msb first. the communication burst is terminated by the serial bus master returning cs high. see figure 7 for details. data is read from the part during a communication burst using sdo. readback may be multidrop (more than one LTC6946 connected in parallel on the serial bus), as sdo is three-stated (hi-z) when cs = 1, or when data is not being read from the part. if the LTC6946 is not used in a multidrop configuration, or if the serial port master is not capable of setting the sdo line level between read sequences, it is recommended to attach a high value resistor of greater than 200k between sdo and gnd to ensure the line returns to a known level during hi-z states. see figure 8 for details. single byte transfers the serial port is arranged as a simple memory map, with status and control available in 12, byte-wide registers. all data bursts are comprised of at least two bytes. the 7 most significant bits of the first byte are the register address, with an lsb of 1 indicating a read from the part, and lsb of 0 indicating a write to the part. the subsequent byte, or bytes, is data from/to the specified register address. see figure 9 for an example of a detailed write sequence, and figure 10 for a read sequence. figure 11 shows an example of two write communication bursts. the first byte of the first burst sent from the serial bus master on sdi contains the destination register address (addr0) and an lsb of 0 indicating a write. the next byte is the data intended for the register at address addr0. cs is then taken high to terminate the transfer. the first byte of the second burst contains the destination register address (addr1) and an lsb indicating a write. the next byte on sdi is the data intended for the register at address addr1. cs is then taken high to terminate the transfer. masterCcs masterCsclk t css t cs t ch data data 6946 f07 t ckl t ckh t css t csh masterCsdi masterCcs masterCsclk LTC6946Csdo hi-z hi-z 6946 f08 8th clock data data t do t do t do t do figure 7. serial port write timing diagram figure 8. serial port read timing diagram
LTC6946 18 6946fa operation multiple byte transfers more efficient data transfer of multiple bytes is accom- plished by using the LTC6946s register address auto- increment feature as shown in figure 12. the serial port master sends the destination register address in the first byte and its data in the second byte as before, but continues sending bytes destined for subsequent registers. byte 1s address is addr0+1, byte 2s address is addr0+2, and so on. if the resister address pointer attempts to increment past 11 (h0b), it is automatically reset to 0. an example of an auto-increment read from the part is shown in figure 13. the first byte of the burst sent from the serial bus master on sdi contains the destination reg- ister address (addr0) and an lsb of 1 indicating a read. once the LTC6946 detects a read burst, it takes sdo out of the hi-z condition and sends data bytes sequentially, a6 a5 a4 a3 a2 7-bit register address hi-z masterCcs masterCsclk masterCsdi LTC6946Csd0 a1 a0 0 d7 d6 d5 d4 d3 d2 d1 d0 8 bits of data 0 = write 6946 f09 16 clocks addr0 + wr hi-z masterCcs masterCsdi LTC6946Csdo byte 0 addr1 + wr byte 1 6946 f11 addr0 + wr hi-z masterCcs masterCsdi LTC6946Csdo byte 0 byte 1 byte 2 6946 f12 figure 9. serial port write sequence figure 10. serial port read sequence figure 11. serial port single byte write figure 12. serial port auto-increment write a6 a5 a4 a3 a2 7-bit register address hi-z hi-z a1 a0 1 d7x d6 d5 d4 d3 d2 d1 d0 dx 8 bits of data 1 = read 6946 f10 masterCcs masterCsclk masterCsdi LTC6946Csdo 16 clocks
LTC6946 19 6946fa operation addr0 + rd dont care hi-z hi-z masterCcs masterCsdi LTC6946Csdo 6946 f13 byte 0 byte 1 byte 2 figure 13. serial port auto-increment read beginning with data from register addr0. the part ignores all other data on sdi until the end of the burst. multidrop configuration several LTC6946s may share the serial bus. in this multidrop configuration, sclk, sdi, and sdo are common between all parts. the serial bus master must use a separate cs for each LTC6946 and ensure that only one device has cs asserted at any time. it is recommended to attach a high value resistor to sdo to ensure the line returns to a known level during hi-z states. serial port registers the memory map of the LTC6946 may be found in table 10, with detailed bit descriptions found in table 11. the register address shown in hexadecimal format under the addr column is used to specify each register. each register is denoted as either read-only (r) or read-write (r/w). the registers default value on device power-up or after a reset is shown at the right. the read-only register at address h00 is used to determine different status flags. these flags may be instantly output on the stat pin by configuring register h01. see the stat output section for more information. the read-only register at address h0b is a rom byte for device indentification. table 10. serial port register contents addr msb [6] [5] [4] [3] [2] [1] lsb r/w default h00 * * unlock alchi alclo lock thi tlo r h01 * * x[5] x[4] x[3] x[2] x[1] x[0] r/w h04 h02 pdall pdpll pdvco pdout pdrefo mtcal omute por r/w h0e h03 bd[3] bd[2] bd[1] bd[0] * * rd[9] rd[8] r/w h30 h04 rd[7] rd[6] rd[5] rd[4] rd[3] rd[2] rd[1] rd[0] r/w h01 h05 nd[15] nd[14] nd[13] nd[12] nd[11] nd[10] nd[9] nd[8] r/w h00 h06 nd[7] nd[6] nd[5] nd[4] nd[3] nd[2] nd[1] nd[0] r/w hfa h07 alcen alcmon alccal alculok * * cal lken r/w h21 h08 bst filt[1] filt[0] rfo[1] rfo[0] od[2] od[1] od[0] r/w hf9 h09 lkwin[1] lkwin[0] lkct[1] lkct[0] cp[3] cp[2] cp[1] cp[0] r/w h9b h0a cpchi cpclo cpmid cpinv cpwide cprst cpup cpdn r/w he4 h0b rev[2] rev[1] rev[0] part[4] part[3] part[2] part[1] part[0] r hxx ? *unused ? varies depending on version
LTC6946 20 6946fa operation stat output the stat output pin is configured with the x[5:0] bits of register h01. these bits are used to bit-wise mask, or enable, the corresponding status flags of status register h00, according to equation 2. the result of this bit-wise boolean operation is then output on the stat pin: stat = or (reg00[5:0] and reg01[5:0]) (2) or expanded: stat = (unlock and x[5]) or (alchi and x[4]) or (alclo and x[3]) or (lock and x[2]) or (thi and x[1]) or (tlo and x[0]) for example, if the application requires stat to go high whenever the alchi, alclo, or thi flags are set, then x[4], x[3], and x[1] should be set to 1, giving a register value of h1a. block power-down control the LTC6946s power-down control bits are located in register h02, described in table 11. different portions of the device may be powered down independently. care must be taken with the lsb of the register, the por (power-on reset) bit. when written to a 1, this bit forces a full reset of the parts digital circuitry to its power-up default state. table 11. serial port register bit field summary bits description default alccal auto enable alc during cal operation 1 alcen always enable alc (override) 1 alchi alc too hi flag alclo alc too low flag alcmon enable alc monitor for status flags only 0 alculok enable alc when pll unlocked 0 bd[3:0] calibration b divider value h3 bst ref buffer boost current 1 cal start vco calibration (auto clears) 0 cp[3:0] cp output current hb cpchi cp enable hi voltage output clamp 1 cpclo cp enable low voltage output clamp 1 cpdn cp pump down only 0 cpinv cp invert phase 0 cpmid cp bias to mid-rail 1 cprst cp three-state 1 cpup cp pump up only 0 cpwide cp extend pulse width 0 filt[1:0] ref input buffer filter h3 lkct[1:0] pll lock cycle count h1 lken pll lock indicator enable 1 lkwin[1:0] pll lock indicator window h2 lock pll lock indicator flag mtcal mutes output during calibration 1 nd[15:0] n divider value (nd[15:0] > 31) h00fa od[2:0] output divider value (0 < od[2:0] < 7) h1 omute mutes rf output 1 part[4:0] part code (h01 for LTC6946-1, h02 for LTC6946-2, h03 for LTC6946-3 version) h01, h02, h03 pdall full chip power down 0 pdout powers down o_div, rf output buffer 0 pdpll powers down ref, refo, r_div, pfd, cpump , n_div 0 pdrefo powers down refo 1 pdvco powers down vco, n_div 0 por force power-on reset 0 rd[9:0] r divider value (rd[9:0] > 0) h001 rev[2:0] rev code h2 rfo[1:0] rf output power h3 thi cp clamp high flag tlo cp clamp low flag unlok pll unlock flag x[5:0] stat output or mask h04
LTC6946 21 6946fa applications information introduction a pll is a complex feedback system that may conceptually be considered a frequency multiplier. the system multiplies the frequency input at ref and outputs a higher frequency at rf . the pfd, charge pump, n divider, and external vco and loop filter form a feedback loop to accurately control the output frequency (see figure 14). the r and o divider are used to set the output frequency resolution. using the above equations, the output frequency resolu- tion f step produced by a unit change in n is given by equation 6: f step = f ref r?o (6) loop filter design a stable pll system requires care in selecting the external loop filter values. the linear technology pllwizard ap- plication, available from www.linear.com, aids in design and simulation of the complete system. the loop design should use the following algorithm: 1. determine the output frequency, f rf , and frequency step size, f step , based on application requirements. using equations 3, 4, 5 and 6, change f ref , n, r, and o until the application frequency constraints are met. use the minimum r value that still satisfies the constraints. then calculate b using equation 1 and table 7. 2. select the open-loop bandwidth, bw, constrained by f pfd . a stable loop requires that bw is less than f pfd by at least a factor of 10. 3. select loop filter component r z and charge pump cur- rent i cp based on bw and the vco gain factor, k vco . bw (in hz) is approximated by the following equation: bw ? i cp ?r z ?k vco 2? ?n (7) or r z = 2? ?bw?n i cp ?k vco where k vco is in hz/v, i cp is in amps, and r z is in ohms. kvco is obtained from the vco tuning sensitivity in the electrical characteristics. use i cp = 11.2ma to lower in- band noise unless component values force a lower setting. r_div n_div r n o_div o f pfd LTC6946 ref (f ref ) f vco k pfd k vco 25 rf (f rf ) 15 cp r z c i c p loop filter lf(s) 6946 f14 tune i cp figure 14. pll loop diagram output frequency when the loop is locked, the frequency f vco (in hz) produced at the output of the vco is determined by the reference frequency, f ref , and the r and n divider values, given by equation 3: f vco = f ref ?n r (3) here, the pfd frequency f pfd produced is given by the following equation: f pfd = f ref r (4) and f vco may be alternatively expressed as: f vco = f pfd ? n the output frequency f rf produced at the output of the o divider is given by equation 5: f rf = f vco o (5)
LTC6946 22 6946fa applications information 4. select loop filter components c i and c p based on bw and r z . a reliable loop can be achieved by using the following equations for the loop capacitors (in farads): c i = 3.5 2? ?bw?r z (8) c p = 1 7? ?bw?r z (9) design and programming example this programming example uses the dc1705a with the LTC6946-3. assume the following parameters of interest: f ref = 20mhz at 7dbm into 50 f step = 125khz f rf = 2.4ghz from the electrical characteristics table: f vco = 3.825ghz to 5.744ghz k vco% = 4.0%hz/v to 6.0%hz/v determining divider values following the loop filter design algorithm, first deter- mine all the divider values. using equations 2, 3, 4 and 5 calculate the following values: o = 2 r = 20mhz/(125khz ? 2) = 80 f pfd = 250khz n = 2 ? 2.4ghz/250khz = 19200 f vco = 4.8ghz also, from equation 1 or table 7 determine b: b = 8 and bd[3:0] = 0 the next step in the algorithm is to determine the open- loop bandwidth. bw should be at least 10 smaller than f pfd . wider loop bandwidths could have lower integrated phase noise, depending on the vco phase noise signature, while narrower bandwidths will likely have lower spurious power. use a factor of 15 for this design example: bw = 250khz 15 = 16.7khz loop filter component selection now set loop filter resistor, r z , and charge pump current, i cp . because the k vco varies over the vcos frequency range, using the k vco geometric mean gives good results. using an i cp of 11.2ma, r z is determined: k vco = 4.8 ? 10 9 ?0.04?0.06 = 235mhz / v r z = 2? ? 16.7k ? 19200 11.2m ? 235m r z = 765 now calculate c i and c p from equations 7 and 8: c i = 3.5 2? ? 16.7k ? 765 = 44nf c p = 1 7? ? 16.7k ? 765 = 3.6nf status output programming this example will use the stat pin to alert the system whenever the LTC6946 generates a fault condition. pro- gram x[5], x[4], x[3], x[1], x[0] = 1 to force the stat pin high whenever any of the unlock, alchi, alclo, thi or tlo flags asserts: reg01 = h3b power register programming for correct pll operation all internal blocks should be enabled, but pdrefo should be set if the refo pin is not being used. omute may remain asserted (or the mute pin held low) until programming is complete. for pdrefo = 1 and omute = 1: reg02 = h0a
LTC6946 23 6946fa applications information divider programming program registers reg03 to reg06 with the previously determined b, r and n divider values. reg03 = h00 reg04 = h50 reg05 = h4b reg06 = h00 vco alc and calibration programming now that all the divider registers are programmed, and assuming that the reference frequency is stable at ref , calibrate the vco. set the alc options (alcmon = 1, alccal = 1) and the lock enable bit (lken = 1) at the same time: reg07 = h63 the LTC6946 will now calibrate its vco. the alc will only be active during the calibration cycle, but the alchi and alclo status conditions will be monitored. reference input settings and output divider programming from table 1, filt = 1 for a 20mhz reference frequency. next, convert 7dbm into v p-p . for a cw tone, use the following equation with r = 50: v p-p ? r ?10 (dbm C21)/20 (10) this gives v p-p = 1.41v, and, according to table 2, set bst = 1. now program reg08, assuming maximum rf output power (rfo[1:0] = 3 according to table 9) and od[2:0] = 2: reg08 = hba lock detect and charge pump current programming next, determine the lock indicator window from f pfd . from table 3, lkwin[1:0] = 3 for a t lww of 90ns. the LTC6946 will consider the loop locked as long as the phase coincidence at the pfd is within 8, as calculated: phase = 360 ? t lww ? f pfd = 360 ? 90n ? 250k ? 8 lkwin[1:0] may be set to a smaller value to be more conservative. however, the inherent phase noise of the loop could cause false unlocks for too small a value. choosing the correct lokcnt depends upon the ratio of the bandwidth of the loop to the pfd frequency (bw/f pfd ). smaller ratios dictate larger lokcnt values. a lokcnt value of 128 will work for our ratio of 1/15. from table 4, lkcnt[1:0] = 1 for 128 counts. using table 5 with the previously selected i cp of 11.2ma, gives cp[3:0] = 11 (hb). this is enough information to program reg09: reg09 = hdb charge pump function programming this example uses the additional voltage clamp features to allow us to monitor fault conditions by setting cpchi = 1 and cpclo = 1. if something occurs and the system can no longer lock to its intended frequency, the charge pump output will move toward either gnd or v cp + , thereby setting either the tlo or thi status flags, respectively. disable all the other charge pump functions (cpmid, cpinv, cprst, cpup and cpdn) to allow the loop to lock: reg0a = hc0 the loop should now lock. now unmute the output by setting omute = 0 (assumes the mute pin is high): reg02 = h08 reference source considerations a high quality signal must be applied to the ref inputs as they provide the frequency reference to the entire pll. as mentioned previously, to achieve the parts in-band phase noise performance, apply a cw signal of at least 6dbm into 50, or a square wave of at least 0.5v p-p with slew rate of at least 40v/s. the LTC6946 may be driven single ended to cmos levels (greater than 2.7v p-p ). apply the reference signal directly without a dc-blocking capacitor at ref + , and bypass ref C to gnd with a 47pf capacitor. the bst bit must also be set to 0, according to guidelines given in table 2.
LTC6946 24 6946fa applications information the LTC6946 achieves an in-band normalized phase noise floor of C226dbc/hz (typical). to calculate its equiva- lent input phase noise floor l m(in) , use the following equation 11: l m(in) = C226 + 10 ? log 10 (f ref ) (11) for example, using a 10mhz reference frequency gives an input phase noise floor of C156dbc/hz. the reference frequency sources phase noise must be at least 3db better than this to prevent limiting the overall system performance. in-band output phase noise the in-band phase noise produced at f rf may be calcu- lated by using equation 12. l m(out) = C226 + 10 s log 10 f pfd () + 20 s log 10 f rf f pfd ? ? ? ? ? ? or l m(out) = C226 + 10 s log 10 f pfd () + 20 s log 10 n o ? ? ? ? ? ? (12) as can be seen, for a given pfd frequency f pfd , the output in-band phase noise increases at a 20db-per-decade rate with the n divider count. so, for a given output frequency f rf , f pfd should be as large as possible (or n should be as small as possible) while still satisfying the applications frequency step size requirements. output phase noise due to 1/f noise in-band phase noise at very low offset frequencies may be influenced by the LTC6946s 1/f noise, depending upon f pfd . use the normalized in-band 1/f noise of C274dbc/ hz with equation 13 to approximate the output 1/f phase noise at a given frequency offset f offset . l m(out-1/f) f offset () = C274 + 20 ? log 10 f rf () C10 ? log 10 f offset () (13) unlike the in-band noise floor l m(out) , the 1/f noise l m(out 1/f) does not change with f pfd , and is not constant over offset frequency. see figure 15 for an example of in-band phase noise for f pfd equal to 3mhz and 100mhz. the total phase noise will be the summation of lm(out) and l m(out 1/f) . figure 15. theoretical in-band phase noise, f rf = 2500mhz offset frequency (hz) 10 phase noise (dbc/hz) C110 C100 100k 6945 f15 C120 C130 100 1k 10k C90 total noise f pfd = 3mhz total noise f pfd = 100mhz 1/f noise contribution rf output matching the rf outputs may be used in either single-ended or dif- ferential configurations. using both rf outputs differentially will result in approximately 3db more output power than single ended. impedance matching to an external load in both cases requires external chokes tied to v rf + . measured rf s-parameters are shown below in table?12 to aid in the design of impedance matching networks. table 12. single-ended rf output impedance frequency (mhz) impedance (ohms) s11 (db) 500 102.8 C j49.7 C6.90 1000 70.2 C j60.1 C6.53 1500 52.4 C j56.2 C6.35 2000 43.6 C j49.2 C6.58 2500 37.9 C j39.6 C7.34 3000 32.7 C j28.2 C8.44 3500 27.9 C j17.8 C8.99 4000 24.3 C j9.4 C8.72 4500 22.2 C j3.3 C8.26 5000 21.6 + j1.9 C8.02 5500 21.8 + j6.6 C7.91 6000 23.1 + j11.4 C8.09 6500 25.7 + j16.9 C8.38 7000 29.3 + j23.0 C8.53 7500 33.5 + j28.4 C8.56 8000 37.9 + j32.6 C8.64
LTC6946 25 6946fa applications information single-ended impedance matching is accomplished using the circuit of figure 16, with component values found in table 13. using smaller inductances than recommended can cause phase noise degradation, especially at lower center frequencies. table 13. suggested single-ended matching component values f rf (mhz) l c (nh) c s (pf) 350 to 1500 180 270 1000 to 5800 68 100 return loss measured on the dc1705a using the above component values is shown in figure 17. a broadband match is achieved using an (l c , c s ) of either (68nh, 100pf) or (180nh, 270pf). however, for maximum output power and best phase noise performance, use the recommended component values of table 13. l c should be a wirewound inductor selected for maximum q factor and srf, such as the coilcraft hp series of chip inductors. the LTC6946s differential rf outputs may be combined using an external balun to drive a single-ended load. the advantages are approximately 3db more output power than each output individually and better 2nd order harmonic performance. for lower frequencies, transmission line (tl) baluns such as the m/a-com mabact0065 and the toko #617db-1673 provide good results. at higher frequencies, surface mount (smt) baluns such as those produced by tdk, anaren, and johanson technology, can be attractive alternatives. see table 14 for recommended balun part numbers versus frequency range. figure 17. single-ended return loss figure 16. single-ended output matching schematic rf +(C) l c c s 50 to 50 load v rf + rf C(+) l c c s 6946 f16 v rf + 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 frequency (ghz) s11 (db) C6 C4 C2 6946 f17 C10 C16 0 C8 C12 C14 68nh, 100pf 180nh, 270pf the listed smt baluns contain internal chokes to bias rf and also provide input-to-output dc isolation. the pin denoted as gnd or dc feed should be connected to the v rf + voltage. figure 18 shows a surface mount baluns connections with a dc feed pin. table 14. suggested baluns f rf (mhz) part number manufacturer type 350 to 900 #617db-1673 toko tl 400 to 600 hhm1589b1 tdk smt 600 to 1400 bd0810j50200 anaren smt 600 to 3000 mabact0065 m/a-com tl 1000 to 2000 hhm1518a3 tdk smt 1400 to 2000 hhm1541e1 tdk smt 1900 to 2300 2450bl15b100e johanson smt 2000 to 2700 hhm1526 tdk smt 3700 to 5100 hhm1583b1 tdk smt 4000 to 6000 hhm1570b1 tdk smt the listed tl baluns do not provide input-to-output dc isolation and must be ac coupled at the output. figure?18 displays rf connections using these baluns.
LTC6946 26 6946fa figure 18. example smt balun connection figure 19. example tl balun connection applications information supply bypassing and pcb layout guidelines care must be taken when creating a pcb layout to mini- mize power supply decoupling and ground inductances. all power supply v + pins should be bypassed directly to the ground plane using a 0.1f ceramic capacitor as close to the pin as possible. multiple vias to the ground plane should be used for all ground connections, including to the power supply decoupling capacitors. the packages exposed pad is a ground connection, and must be soldered directly to the pcb land. the pcb land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance (see figure 20 for an example). see qfn pack- age users guide, page 8, on linear technology websites packaging information page for specific recommendations concerning land patterns and land via solder masks. a link is provided below. http://www.linear.com/designtools/packaging/index.jsp figure 20. example exposed pad land pattern reference signal routing, spurious and phase noise the charge pump operates at the pfds comparison frequency f pfd . the resultant output spurious energy is small and is further reduced by the loop filter before it modulates the vco frequency. however, improper pcb layout can degrade the LTC6946s inherent spurious performance. care must be taken to prevent the reference signal f ref from coupling onto the vcos tune line, or into other loop filter signals. example suggestions are the following. 1. do not share power supply decoupling capacitors between same voltage power supply pins. 2. use separate ground vias for each power supply de- coupling capacitor, especially those connected to v ref + , v cp + , and v vco + . 3. physically separate the reference frequency signal from the loop filter and vco. 4. do not place a trace between the cm a , cm b and cm c pads underneath the package as worse phase noise could result. LTC6946 v rf + rf C rf + to 50 load 6946 f18 12 balun 2 3 1 5 4 6 11 balun pin configuration 1 2 3 4 5 6 unbalanced port gnd or dc feed balanced port balanced port gnd nc LTC6946 v rf + rf C rf + to 50 load pri sec 6946 f19 12 11 6946 f20
LTC6946 27 6946fa applications information LTC6946-2 driving a modulator mute gnd rf C rf + v rf + bb ref + ref C v ref + cp v cp + gnd v refo + refo stat cs sclk sdi sdo v d + v vco + gnd cm a cm b cm c gnd tb tune LTC6946-2 spi bus 3.3v 470pf 51.1 + 15 5v r z 1f 3.3v loop compensation component values are application specific depending on the lo frequency range and step size and the phase noise of the reference c i 0.01f 0.1f 3.3v 3.3v 1f 0.01f 0.01f 2.2f c p 0.01f 470pf 10mhz reference 3.3v 3.3v the unused rf C output is available to drive another 50 load 68nh lom lo = 1950mhz toko 4dfb-1950l-10 3.3v v cc2 rf gndrf bbpi bbmi bbpq bbmq lop gnd linopt 6946 ta02 ltc5588-1 v cc1 1nf 68nh 0.1f 4.7f 3.3v 1nf 50 1 1.3 1nf 50 10nf 1810mhz 140mhz vga 1nf 4.7f 0 90 baseband generator en en i-dac q-dac ltc2630 pa rf frequency (mhz) 1802.5 C120 power in 30khz bw (dbm) C90 C90 C80 C70 C60 C50 1807.5 1812.5 6946 ta02b C40 C30 measured signal measurement noise floor C110 1817.5 ?C80dbc measured w-cdma acpr (3.84mhz bandwidth) LTC6946-2 modulator application phase noise offset frequency (hz) C130 C140 phase noise (dbc/hz) C110 C90 C150 C120 C100 100 10k 100k 1m 10m 6946 ta02c C160 1k rms noise = 0.281 f rf = 1950mhz f pfd = 2mhz od = 2 f step = 1mhz
LTC6946 28 6946fa please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. package description ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 p 0.10 (2 sides) 2.50 ref 5.00 p 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 27 28 1 2 bottom viewexposed pad 3.50 ref 0.75 p 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 s 45o chamfer 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 p0.05 0.25 p0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 p 0.05 5.50 p 0.05 2.65 p 0.05 3.10 p 0.05 4.50 p 0.05 package outline 2.65 p 0.10 3.65 p 0.10 3.65 p 0.05
LTC6946 29 6946fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/11 add i ol and remove max value, remove max value for i oh 4 revise values on block diagram 11
LTC6946 30 6946fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2011 lt 1111 rev a ? printed in usa related parts typical application part number description comments ltc5540/ltc5541 ltc5542/ltc5543 high dynamic range down mixers 8db conversion gain, 26.4dbm iip3, 9.6db nf, 600mhz to 4ghz ltc5590/ltc5591 ltc5592/ltc5593 high linearity dual mixers 600mhz to 4.5ghz, 8.5db gain, 26.2dbm iip3, 9.9db nf ltc5569 broadband dual mixer 300mhz to 4ghz, 26.8db iip3, 2db gain, 11.7db nf, 600mw power ltc5588-1 ultrahigh oip3 i/q modulator 200mhz to 6ghz, 31dbm oip3, C160.6dbm/hz noise floor lt ? 5575 direct conversion i/q demodulator 800mhz to 2.7ghz, 22.6dbm iip3, 60dbm iip3, 12.7db nf LTC6946-2 driving a passive downconverting mixer mute gnd rf C rf + v rf + bb ref + ref C v ref + cp v cp + gnd v refo + refo stat cs sclk sdi sdo v d + v vco + gnd cm a cm b cm c gnd tb tune LTC6946-2 spi bus 3.3v 470pf 51.1 + 15 5v r z 1f 3.3v loop compensation component values are application specific depending on the lo frequency range and step size and the phase noise of the reference c i 0.01f 0.1f 3.3v 3.3v 1f 0.01f 0.01f 2.2f c p 0.01f balun tdk hhm1525 3.3v lo2 lo1 lobias losel v cc3 ifbias ifgnd shdn gndgnd gnd ltc5541 gnd gnd v cc2 ct rf v cc1 1f 3.3v 30nh if + 150nh if C 470pf 10mhz reference toko 4dfb-1842n-10 22pf 22pf 1f 3.3v 3.3v lo = 1842mhz 0.1f adc 150nh 1nf 140mhz saw 140mhz bpf 1.5pf 2.2pf lna image bpf rf in 1952mhz to 2012mhz 3.3v 22pf 1nf 6946 ta03 rf blocker power (dbm) C20 9 ssb noise figure (db) 10 12 13 14 C10 0 5 18 6946 ta03b 11 C15 C5 15 16 17 rf = 1982mhz blocker = 2082mhz lo = LTC6946-2 lo = clean lab source ltc5541 noise figure vs blocker power and lo signal source LTC6946-2 mixer application phase noise offset frequency (hz) C130 C140 phase noise (dbc/hz) C110 C90 C150 C120 C100 100 10k 100k 1m 10m 6946 ta03c C160 1k rms noise = 0.270 f rf = 1842mhz f pfd = 2mhz od = 2 f step = 1mhz

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